发明授权
- 专利标题: Method and apparatus for a frequency detection circuit for use in a phase locked loop
- 专利标题(中): 用于锁相环的频率检测电路的方法和装置
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申请号: US349586申请日: 1994-12-05
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公开(公告)号: US5530383A公开(公告)日: 1996-06-25
- 发明人: Michael R. May
- 申请人: Michael R. May
- 专利权人: Motorola Solutions Inc
- 当前专利权人: Motorola Solutions Inc
- 主分类号: H03L7/095
- IPC分类号: H03L7/095 ; H03L7/097 ; H03D3/24
摘要:
A frequency lock indicator (10) comprises a first delay (14), second delay (20), first sampler (24), second sampler (28), third sampler (32), fourth sampler (34), and lock indicator (36). The first delay (14) delays a rising edge of a frequency reference (12) which clocks the first sampler (24) on a rising edge and the third sampler (32) on a falling edge. The second delay (20) delays a rising edge of a feedback signal (18) to produce a delayed feedback signal (22) which clocks the second sampler (28) on a rising edge and the fourth sampler (34) on a falling edge. The first and third samplers sample an up-pump signal (26) and the second and fourth samplers sample a down-pump signal (30). The lock indicator (36) produces a lock indication signal (38) when the sampled up-pump signal substantially equal to the sampled down-pump signal.
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