发明授权
US5541505A Testing integrated circuits by consolidating a plurality of digital
signals as a multilevel signal
失效
通过将多个数字信号合并为多电平信号来测试集成电路
- 专利标题: Testing integrated circuits by consolidating a plurality of digital signals as a multilevel signal
- 专利标题(中): 通过将多个数字信号合并为多电平信号来测试集成电路
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申请号: US121102申请日: 1993-09-14
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公开(公告)号: US5541505A公开(公告)日: 1996-07-30
- 发明人: Hideo Azumai
- 申请人: Hideo Azumai
- 申请人地址: JPX Osaka
- 专利权人: Mega Chips Corporation
- 当前专利权人: Mega Chips Corporation
- 当前专利权人地址: JPX Osaka
- 优先权: JPX3-141101 19910515
- 主分类号: G01R31/3185
- IPC分类号: G01R31/3185 ; G06F11/22 ; G01R31/00
摘要:
An apparatus for testing a semiconductor integrated circuit includes a plurality of probe lines and a plurality of sense lines which intersect each other to thereby define a plurality of intersections thereby as electrically isolated from each other. An electronic switch device is provided for each intersection for producing a multilevel signal, on an associated sense line, having one of a predetermined number of voltage levels corresponding to various combinations definable by a predetermined number of binary numbers supplied to test points from logic elements to be tested.In a four test point embodiment, four test points are arranged such that each test point is located in a corresponding one of four quadrants defined by a pair of probe and sense lines intersecting each other. Preferably, the integrated circuit is in the form of a gate array.
公开/授权文献
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