发明授权
US5565790A ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET 失效
ESD保护电路与场晶体管钳位和电阻在钳位触发FET的栅极电路中

ESD protection circuit with field transistor clamp and resistor in the
gate circuit of a clamp triggering FET
摘要:
An improved ESD protection circuit of the type having a field transistor connected as a clamp between ground and a pad to be protected and an FET trigger circuit that is connected between ground and a node where the protected circuits are connected. A resistor interconnects the pad and the node. The trigger FET turns on when a high ESD voltage causes avalanche breakdown and charge carriers from the trigger FET turn on the field transistor clamp. Before the field transistor clamp turns on, oxide breakdown in the gate oxide of the FET occurs. A resistor is connected between the gate electrode and ground to limit the current through the oxide during the time for the avalanche to develop and for the clamp to turn on.
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