发明授权
US5567988A Integrated circuit interconnect structure with back reflection
suppressing electronic "speed bumps"
失效
集成电路互连结构,具有背反射抑制电子“速度凸块”
- 专利标题: Integrated circuit interconnect structure with back reflection suppressing electronic "speed bumps"
- 专利标题(中): 集成电路互连结构,具有背反射抑制电子“速度凸块”
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申请号: US483113申请日: 1995-06-07
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公开(公告)号: US5567988A公开(公告)日: 1996-10-22
- 发明人: Michael D. Rostoker , Nicholas F. Pasch
- 申请人: Michael D. Rostoker , Nicholas F. Pasch
- 申请人地址: CA Milpitas
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 当前专利权人地址: CA Milpitas
- 主分类号: H01L23/522
- IPC分类号: H01L23/522 ; H01L23/48 ; H01L23/52 ; H01L29/40
摘要:
A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.
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