发明授权
- 专利标题: Semiconductor memory
- 专利标题(中): 半导体存储器
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申请号: US533550申请日: 1995-09-25
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公开(公告)号: US5574687A公开(公告)日: 1996-11-12
- 发明人: Yasunobu Nakase
- 申请人: Yasunobu Nakase
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX7-159442 19950626
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C7/12 ; G11C11/419 ; G11C7/00
摘要:
There is disclosed a rapidly and correctly readable semiconductor device wherein a clamping transistor (Pcr.sub.-- 0) having a threshold voltage (Vthp) precharges a pair of bit lines (BIT.sub.-- 0, BIT.sub.-- 1) at a precharge potential (VDD-.vertline.Vthp.vertline.) when transistors (Pprc.sub.-- 0, Pprc.sub.-- 1) are conducting, and a write circuit (3) includes a clamping transistor (Pcr.sub.-- 1) having the same threshold voltage (Vthp) as the clamping transistor (Pcr.sub.-- 0), and inverters (23, 24) responsive to input data (DIN.sub.-- 0, DIN.sub.-- 1) for outputting signals which are "H" at the precharge potential (VDD-.vertline.Vthp.vertline.) and "L" at the ground potential to a pair of write input lines (WD.sub.-- 0, WD.sub.-- 1), respectively.
公开/授权文献
- US3956668A Vertical deflection circuit 公开/授权日:1976-05-11
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