发明授权
US5574687A Semiconductor memory 失效
半导体存储器

Semiconductor memory
摘要:
There is disclosed a rapidly and correctly readable semiconductor device wherein a clamping transistor (Pcr.sub.-- 0) having a threshold voltage (Vthp) precharges a pair of bit lines (BIT.sub.-- 0, BIT.sub.-- 1) at a precharge potential (VDD-.vertline.Vthp.vertline.) when transistors (Pprc.sub.-- 0, Pprc.sub.-- 1) are conducting, and a write circuit (3) includes a clamping transistor (Pcr.sub.-- 1) having the same threshold voltage (Vthp) as the clamping transistor (Pcr.sub.-- 0), and inverters (23, 24) responsive to input data (DIN.sub.-- 0, DIN.sub.-- 1) for outputting signals which are "H" at the precharge potential (VDD-.vertline.Vthp.vertline.) and "L" at the ground potential to a pair of write input lines (WD.sub.-- 0, WD.sub.-- 1), respectively.
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