- 专利标题： Storage circuitry using sense amplifier shared between memories of differing number of rows
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申请号： US482384申请日： 1995-06-07
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公开(公告)号： US5579273A公开(公告)日： 1996-11-26
- 发明人: Jimmie D. Childers , Seiichi Yamamoto , Masanari Takeyasu
- 申请人： Jimmie D. Childers , Seiichi Yamamoto , Masanari Takeyasu
- 申请人地址： TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： TX Dallas
- 主分类号： G11C7/06
- IPC分类号： G11C7/06 ; G11C11/4091
摘要：
A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a read/write operation, or to wait until a calculation is completed.
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