Invention Grant
US5587807A Apparatus for processing digital video data with error correction parity
comprising error concealment means
失效
用于处理具有错误校正奇偶校验的数字视频数据的装置,包括错误隐藏装置
- Patent Title: Apparatus for processing digital video data with error correction parity comprising error concealment means
- Patent Title (中): 用于处理具有错误校正奇偶校验的数字视频数据的装置,包括错误隐藏装置
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Application No.: US317793Application Date: 1994-10-04
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Publication No.: US5587807APublication Date: 1996-12-24
- Inventor: Takeshi Ootsuka , Masaaki Higashida
- Applicant: Takeshi Ootsuka , Masaaki Higashida
- Applicant Address: JPX Osaka
- Assignee: Matsushita Electric Industrial Co., Ltd.
- Current Assignee: Matsushita Electric Industrial Co., Ltd.
- Current Assignee Address: JPX Osaka
- Priority: JPX5-249030 19931005
- Main IPC: H04N5/92
- IPC: H04N5/92 ; G11B20/12 ; G11B20/18 ; H04N5/926 ; H04N5/94 ; H04N5/76
Abstract:
In an apparatus for processing input N-bit digital video data with an error correction parity, the input N-bit digital video data includes each one sample of higher-order-N-bit data and a plurality of samples of lower-order-(M-N)-bit data, wherein M>N. An error correction circuit corrects an error of input N-bit digital video data, outputs error-corrected N-bit digital video data, and generates an error detection signal representing an error which can not be corrected. Further, a data combining circuit converts the error-corrected N-bit digital video data into M-bit digital video data, and an error classifying circuit classifies the error detection signal into a first error detection signal representing an error of the each one sample of the higher-order-N-bit data and a second error detection signal representing an error of the plurality of samples of the lower-order-(M-N)-bit data. An error concealment circuit performs an error concealment process for the converted M-bit digital video data based on only the first error detection signal.
Public/Granted literature
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