发明授权
US5590049A Method and system for user programmable design verification for printed
circuit boards and multichip modules
失效
用于印刷电路板和多芯片模块的用户可编程设计验证的方法和系统
- 专利标题： Method and system for user programmable design verification for printed circuit boards and multichip modules
- 专利标题（中）： 用于印刷电路板和多芯片模块的用户可编程设计验证的方法和系统
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申请号： US302329申请日： 1994-09-07
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公开(公告)号： US5590049A公开(公告)日： 1996-12-31
- 发明人: Sandeep Arora
- 申请人： Sandeep Arora
- 申请人地址： CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： CA San Jose
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method and system for verifying design constraints on printed circuit boards and multichip modules provides for user programmability and design of new constraints and applicable verification procedures for verifying the constraints. New constraints are defined, identifying various attributes dealing with the circuit elements to which the constraint is applied, and precedence of the constraint with respect to existing constraints on circuit element. A verification procedure is defined for the constraint, and the verification procedure is registered in a constraint verification library such that it can be retrieved when an circuit element is supplied to a verification engine for verification of applicable design constraints on the circuit element.
公开/授权文献
- US4952161A Card connector 公开/授权日：1990-08-28
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