Invention Grant
US5590065A Digital decimation filter for delta sigma analog-to-digital conversion
with reduced hardware compelexity
失效
数字抽取滤波器，用于减少硬件复合度的西格玛模数转换
- Patent Title: Digital decimation filter for delta sigma analog-to-digital conversion with reduced hardware compelexity
- Patent Title (中): 数字抽取滤波器，用于减少硬件复合度的西格玛模数转换
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Application No.: US288624Application Date: 1994-08-10
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Publication No.: US5590065APublication Date: 1996-12-31
- Inventor: Kun Lin
- Applicant: Kun Lin
- Applicant Address: TX Ausitn
- Assignee: Crystal Semiconductor Corporation
- Current Assignee: Crystal Semiconductor Corporation
- Current Assignee Address: TX Ausitn
- Main IPC: H03H17/02
- IPC: H03H17/02 ; H03H17/04 ; G06F17/10
Abstract:
A decimation filter includes a plurality of integration stages, at least one decimation stage, and a plurality of differentiation stages followed by a FIR filter. At least one of the integration stages, the decimation stage, and the differentiator stages, and the FIR filter are implemented in a single ALU which includes a single adder, a ROM, and a RAM. The different sampling rates of the integrator stage and the FIR filter requires the storage of intermediate results in RAM of the FIR filter calculations.
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