A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide. Active regions in the silicon substrate, implanted with a conductivity-imparting dopant, are formed under the second insulating layer but are horizontally a distance from the first insulating structure.