发明授权
US5631858A System for obtaining strict solution in accordance with accuracy of
approximate solutions
失效
根据近似解决方案的准确度获得严格解决方案的系统
- 专利标题: System for obtaining strict solution in accordance with accuracy of approximate solutions
- 专利标题(中): 根据近似解决方案的准确度获得严格解决方案的系统
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申请号: US89103申请日: 1993-08-12
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公开(公告)号: US5631858A公开(公告)日: 1997-05-20
- 发明人: Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
- 申请人: Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
- 申请人地址: JPX Tokyo JPX Ibaraki-ken
- 专利权人: Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人地址: JPX Tokyo JPX Ibaraki-ken
- 优先权: JPX63-277242 19881104; JPX63-290248 19881118; JPX63-309968 19881209
- 主分类号: G06F7/52
- IPC分类号: G06F7/52 ; G06F7/552 ; G06F7/57 ; G06F7/38
摘要:
A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
公开/授权文献
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