A conversion cache circuit, interfacing RISC busses to CISC peripheral circuits, provides master/slave Write and Read operations in a shared memory (130) and in the internal registers of the processor of said peripheral circuits (210). It enables RISC processor to Write and Read in the internal registers of the 8-bit processor in a salve operation while the 32-bit processor may perform the Write or Read operations to the shared memory through the conversion cache circuit in a master mode. The 32-bit processor may have access directly to the memory through its own direct access memory mechanism.