发明授权
US5638333A Bit line sensing circuit and method of a semiconductor memory device 失效
半导体存储器件的位线检测电路和方法

Bit line sensing circuit and method of a semiconductor memory device
摘要:
A bit line sensing circuit of a semiconductor memory device having NMOS and PMOS sense amps connected to a bit line includes a variable delay path for variably controlling an interval of the operating time between the NMOS and PMOS sense amps in response to a power voltage sensing signal generated by sensing a power voltage level.
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