发明授权
- 专利标题: Methods of forming BiCMOS semiconductor devices
- 专利标题(中): 形成BiCMOS半导体器件的方法
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申请号: US688998申请日: 1996-08-01
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公开(公告)号: US5643810A公开(公告)日: 1997-07-01
- 发明人: Young-Soo Jang
- 申请人: Young-Soo Jang
- 申请人地址: KRX Suwon
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KRX Suwon
- 优先权: KRX95-34194 19951006
- 主分类号: H01L21/334
- IPC分类号: H01L21/334 ; H01L21/8222 ; H01L21/8248 ; H01L21/8249 ; H01L27/06 ; H01L21/265
摘要:
Methods of forming BiCMOS semiconductor devices include steps for forming bird's beak shaped oxide extensions between the gate electrodes and drain and source regions of CMOS devices to inhibit drain leakage currents and reduce gate-to-drain capacitance. These methods also include steps for forming bird's beak shaped oxide extensions at the emitter-base junctions of BJTs to reduce hot carrier induced P-N junction breakdown. A preferred method includes the steps of forming a gate electrode of a field effect transistor on a face of a semiconductor substrate and then forming self-aligned source and drain regions in the substrate using the gate electrode as a mask. A first conductive layer is then formed on the source and drain regions and used to diffuse dopants into the source and drain regions to increase the conductivity therein. Simultaneously with this diffusion step, the ends of the gate electrode and the first conductive layer are oxidized to form first bird's beak shaped oxide extensions between the gate electrode and the source and drain regions. These first bird's beak shaped oxide extensions are preferably formed to reduce drain leakage currents and gate-to-source capacitance by, among other things, reducing the electric field between the drain-side end of the gate electrode and the drain region. The first conductive layer can also be etched back into discrete intermediate source and drain contact regions to facilitate the subsequent formation of source and drain electrodes in electrical contact with the source and drain regions. Similar steps can also be performed to simultaneously form bipolar junction transistors adjacent the field effect transistors.
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