The memory cells of a read-only memory are connected in parallel between adjacent bus-bit lines. The selection of tile sub-bit lines is through a selector logic decoder. The decoder has many rows of MOSFETs connected in series. Only one of MOSFETs in a row between an adjacent bit line bus and a virtual ground bus is active and controllable by a sub-word line selection signal with other MOSFETs non-conducting and connected between two adjacent sub-bit lines. These active MOSFETs in different rows are connected in series. One of these active MOSFETs is coupled to a main bit line, and another of these active MOSFETs is coupled to a virtual ground. When the active MOSFET is open, the main bit line signal and the virtual signal appear between the corresponding memory cells between these two corresponding sub-bit lines and are sensed. With this structure, the accessed memory cell is coupled between the main bit line and the virtual ground line through a number of series MOSFETs. These series MOSFETs isolate the memory cell from the main bit line, and reduces the undesirable transient lowering of the bit line signal due to parasitic capacitance which may otherwise give rise to error and slow down the speed.