发明授权
US5677554A FET having a dielectrically isolated gate connect 失效
具有介电隔离栅极的FET连接

FET having a dielectrically isolated gate connect
摘要:
A HIGFET having a gate with a pad which is isolated from the FET heterostructure wafer by a dielectric layer to minimize leakage current between the gate and the wafer. The method of production of this device involves application of the gate metal only over the active area of the FET and a photo resist covering on the gate metal. The wafer, including the area covered by the photo resist, is covered with the dielectric layer. The photo resist layer is removed along with the dielectric layer from over the gate metal. Another layer of gate metal is formed on the preexisting gate metal including a gate pad on part of the remaining dielectric layer.
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