An electronic circuit has reduced controller memory requirements for multiple sequential instructions. The electronic circuit includes: a controller memory (1258) with addressable storage locations; a program counter (1548); control logic (1586) for receiving control information from an addressable storage location of the controller memory for performing logical operations on the control information and generating a control signal (1609) responsive to the control information; a repeat counter (1294) for receiving a repeat instruction signal from the controller memory (1258) and for sending a hold count signal (1233) to the program counter (1584) and the control logic (1586) such that the program counter (1584) continues to select the same addressable storage location and the control logic (586) repeats sending the control signal (1609); and a register address counter (1290) for receiving the control signal from the control logic (1586), the hold count signal (1233) from the repeat counter (1294) and a register address signal (1604) from the controller memory. The register address signal stored in the register address counter (1290) points to one of a plurality of registers. The register address counter (1290) receives and stores the address signal if the repeat counter (1294) fail to send the hold count signal and increments the register address signal to point to a next consecutive register if the repeat counter (1294) sends the hold count signal.