发明授权
- 专利标题: Semiconductor memory device capable of electrically erasing and writing information and a manufacturing method of the same
- 专利标题(中): 能够电擦除和写入信息的半导体存储器件及其制造方法
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申请号: US480701申请日: 1995-06-07
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公开(公告)号: US5683923A公开(公告)日: 1997-11-04
- 发明人: Masahiro Shimizu , Masayoshi Shirahata , Takashi Kuroi , Takehisa Yamaguchi
- 申请人: Masahiro Shimizu , Masayoshi Shirahata , Takashi Kuroi , Takehisa Yamaguchi
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX5-060369 19930319; JPX5-097852 19930423
- 主分类号: H01L21/8247
- IPC分类号: H01L21/8247 ; H01L27/115 ; H01L29/788 ; H01L29/792 ; H01L21/265
摘要:
A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5. Therefore, an electric field, which is generated across the floating gate electrode 5 and the drain diffusion region 9 in an unselected cell during writing of data, is weakened, as compared with the prior art, and the drain disturb phenomenon due to F-N tunneling is effectively prevented.
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