A computer system which includes a page mode memory in which a particular piece of data is accessed by first supplying a page or row address, then supplying a column address. These addresses are input to the memory by row address strobe (RAS) signals and column address strobe (CAS) signals. The RAS signals are determined by comparing input CPU addresses with row starting address information stored in registers, each of which corresponds to a memory socket in which a memory module may be installed. An algorithm is described for initializing the memory and its memory controller, including a determination of the starting address information.