发明授权
US5689673A Apparatus and method for controlling instruction flow by using a matrix
of transmission gates in super-scaler microprocessor and selectively
delaying microprocessor instruction execution based on resource
availability
失效
用于通过使用超级缩放微处理器中的传输门矩阵来控制指令流的装置和方法，并且基于资源可用性选择性地延迟微处理器指令执行
- 专利标题： Apparatus and method for controlling instruction flow by using a matrix of transmission gates in super-scaler microprocessor and selectively delaying microprocessor instruction execution based on resource availability
- 专利标题（中）： 用于通过使用超级缩放微处理器中的传输门矩阵来控制指令流的装置和方法，并且基于资源可用性选择性地延迟微处理器指令执行
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申请号： US388602申请日： 1995-02-14
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公开(公告)号： US5689673A公开(公告)日： 1997-11-18
- 发明人: Takeshi Kitahara
- 申请人： Takeshi Kitahara
- 申请人地址： CA Campbell
- 专利权人： Hal Computer Systems, Inc.
- 当前专利权人： Hal Computer Systems, Inc.
- 当前专利权人地址： CA Campbell
- 主分类号： G06F9/38
- IPC分类号： G06F9/38 ; G06F13/14 ; G06F9/22 ; G06F9/30
摘要：
An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of signals indicating how many execution units are available with a number of signals indicating how many execution units are required. The circuit is a matrix of transmission gates which propagate signals through, or shift signals between, various signal paths for available resources, depending on the signals requesting the executing units. A number of output gates suppress the execution of instruction signals where an execution unit is requested but none are available.
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