发明授权
US5691115A Exposure method, aligner, and method of manufacturing semiconductor
integrated circuit devices
失效
半导体集成电路器件的曝光方法，对准器及其制造方法
- 专利标题： Exposure method, aligner, and method of manufacturing semiconductor integrated circuit devices
- 专利标题（中）： 半导体集成电路器件的曝光方法，对准器及其制造方法
-
申请号： US546313申请日： 1995-10-20
-
公开(公告)号： US5691115A公开(公告)日： 1997-11-25
- 发明人: Yoshihiko Okamoto , Tsuneo Terasawa , Akira Imai , Norio Hasegawa , Shinji Okazaki
- 申请人： Yoshihiko Okamoto , Tsuneo Terasawa , Akira Imai , Norio Hasegawa , Shinji Okazaki
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX6-262938 19941026; JPX7-43861 19950303; JPX7-223727 19950831
- 主分类号： G03F1/00
- IPC分类号： G03F1/00 ; G03F1/26 ; G03F1/30 ; G03F1/60 ; G03F7/20 ; G03F9/00 ; G03C5/00
摘要：
To prevent positional shifts of the image forming plane during the exposure process using the two-layer phase shift mask, the height position of the semiconductor wafer 14 is moved in the optical axis direction according to the mask substrate thickness of the second component mask 12b, prior to performing the exposure process which uses the stacked-layer mask 12 that comprises a first component mask 12a formed with a pattern of light-shielding areas and light-transmitting areas and a second component mask 12b formed with a phase shift pattern to produce a phase shift in the transmitted light.