发明授权
US5696639A Sampled amplitude read channel employing interpolated timing recovery
失效
采用内插时序恢复的采样幅度读取通道
- 专利标题: Sampled amplitude read channel employing interpolated timing recovery
- 专利标题(中): 采用内插时序恢复的采样幅度读取通道
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申请号: US440508申请日: 1995-05-12
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公开(公告)号: US5696639A公开(公告)日: 1997-12-09
- 发明人: Mark S. Spurbeck , Richard T. Behrens , German S. Feyh
- 申请人: Mark S. Spurbeck , Richard T. Behrens , German S. Feyh
- 申请人地址: CA Fremont
- 专利权人: Cirrus Logic, Inc.
- 当前专利权人: Cirrus Logic, Inc.
- 当前专利权人地址: CA Fremont
- 主分类号: G11B20/10
- IPC分类号: G11B20/10 ; G11B20/12 ; G11B20/14 ; H04L7/02 ; H04L7/04 ; C11B5/09
摘要:
A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. The channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector for detecting the digital data from the interpolated sample values.
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