发明授权
US5726942A Hierarchical encoder including timing and data detection devices for a
content addressable memory
失效
分层编码器,包括用于内容可寻址存储器的定时和数据检测装置
- 专利标题: Hierarchical encoder including timing and data detection devices for a content addressable memory
- 专利标题(中): 分层编码器,包括用于内容可寻址存储器的定时和数据检测装置
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申请号: US760292申请日: 1996-12-04
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公开(公告)号: US5726942A公开(公告)日: 1998-03-10
- 发明人: Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
- 申请人: Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
- 申请人地址: JPX Hyogo
- 专利权人: Kawasaki Steel Corporation
- 当前专利权人: Kawasaki Steel Corporation
- 当前专利权人地址: JPX Hyogo
- 优先权: JPX4-003405 19920110; JPX4-043963 19920228; JPX4-169258 19920626; JPX4-174314 19920701; JPX4-181194 19920708
- 主分类号: G06F7/74
- IPC分类号: G06F7/74 ; G06F17/30 ; G11C15/04 ; G11C7/06
摘要:
A encoder has a prefetch circuit or a flag data sense circuit built into the priority encoder provided for a CAM block. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and this makes the encoder best suitable for a large capacity CAM which is required to operate at high speed. Moreover, a semiconductor integrated circuit of the present invention detects the differential current between the current flowing through one signal line and the reference current flowing through the other signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock, and it can operate as the timing control circuit to previously notify the encode termination of the hit signal in the subblock of the encoder described above. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed. Moreover, a dynamic sense amplifier is able to operate with a great operating margin.
公开/授权文献
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