• 专利标题: Method of bonding a III-V group compound semiconductor layer on a silicon substrate
  • 申请号: US405104
    申请日: 1995-03-16
  • 公开(公告)号: US5728623A
    公开(公告)日: 1998-03-17
  • 发明人: Kazuo Mori
  • 申请人: Kazuo Mori
  • 申请人地址: JPX Tokyo
  • 专利权人: NEC Corporation
  • 当前专利权人: NEC Corporation
  • 当前专利权人地址: JPX Tokyo
  • 优先权: JPX6-045828 19940316; JPX6-303707 19941207
  • 主分类号: H01L21/20
  • IPC分类号: H01L21/20 H01L21/02 H01L21/18 H01L21/30
Method of bonding a III-V group compound semiconductor layer on a
silicon substrate
摘要:
Prior to a heat treatment for bonding a III-V group compound semiconductor layer on a silicon substrate, a thermal stress relaxation layer is provided between the silicon layer and the III-V group compound semiconductor layer thermal stress relaxation layer, having a thermal expansion coefficient equal or near to the thermal expansion coefficient of the III-V group compound semiconductor layer and having a rigidity coefficient being sufficiently large to suppress generation of any crystal defects in the III-V group compound semiconductor layer due to a thermal stress generated in the heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between the III-V group compound semiconductor layer and the silicon layer.
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