发明授权
US5734290A Charge pumping circuit having cascaded stages receiving two clock signals
失效
具有级联级的电荷泵浦电路接收两个时钟信号
- 专利标题: Charge pumping circuit having cascaded stages receiving two clock signals
- 专利标题(中): 具有级联级的电荷泵浦电路接收两个时钟信号
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申请号: US616882申请日: 1996-03-15
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公开(公告)号: US5734290A公开(公告)日: 1998-03-31
- 发明人: Kuen-Long Chang , Jieh-Tsorng Wu
- 申请人: Kuen-Long Chang , Jieh-Tsorng Wu
- 申请人地址: TWX
- 专利权人: National Science Council of R.O.C.
- 当前专利权人: National Science Council of R.O.C.
- 当前专利权人地址: TWX
- 主分类号: H02M3/07
- IPC分类号: H02M3/07 ; G05F1/10
摘要:
A charge pumping circuit includes a plurality of cascaded voltage gain circuit stages. Each circuit stage has an switching transistor with a source connected electrically to a drain of the transistor of an immediately succeeding one of the circuit stages, and a gate connected electrically to the source of the transistor of the immediately succeeding one of the circuit stages, and a capacitor. The capacitor of odd ones of the circuit stages is connected electrically across a first clock and the source of the transistor of the respective circuit stage. The capacitor of even ones of the circuit stages is connected electrically across a second clock, which is out of phase with the first clock, and the source of the transistor of the respective circuit stage. An output transistor has a drain connected electrically to the source of the transistor of a last voltage gain circuit stage, a source serving as an output terminal of the charge pumping circuit, and a gate connected electrically to the drain of the output transistor. An output capacitor is connected electrically across the source of the output transistor and the first clock when the total number of the voltage gain circuit stages is an even number and across the source of the output transistor and the second clock when the total number of the voltage gain circuit stages is an odd number.
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