发明授权
US5740402A Conflict resolution in interleaved memory systems with multiple parallel accesses 失效
具有多个并行访问的交错存储器系统中的冲突解决

Conflict resolution in interleaved memory systems with multiple parallel
accesses
摘要:
A conflict resolution system for interleaved memories in processors capable of issuing multiple independent memory operations per cycle. The conflict resolution system includes an address bellow for temporarily storing memory requests, and cross-connect switches to variously route multiple parallel memory requests to multiple memory banks. A control logic block controls the address bellow and the cross-connect switches to reorder the sequence of memory requests to avoid conflicts. The reordering removes conflicts and increases the occurrence of alternating memory requests that can issue simultaneously.
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