发明授权
US5745843A Selective call receivers with integer divide synthesizers for achieving
fast-lock time
失效
具有整数除法合成器的选择性呼叫接收器，实现快速锁定时间
- 专利标题： Selective call receivers with integer divide synthesizers for achieving fast-lock time
- 专利标题（中）： 具有整数除法合成器的选择性呼叫接收器，实现快速锁定时间
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申请号： US511159申请日： 1995-08-04
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公开(公告)号： US5745843A公开(公告)日： 1998-04-28
- 发明人: John David Wetters , Raul Salvi
- 申请人： John David Wetters , Raul Salvi
- 申请人地址： Schaumburg
- 专利权人： Motorola, Inc.
- 当前专利权人： Motorola, Inc.
- 当前专利权人地址： Schaumburg
- 主分类号： H03L7/23
- IPC分类号： H03L7/23 ; H04B1/50
摘要：
A selective call receiver (100) for receiving and transmitting paging signals has a transceiver (104) having an integer divide synthesizer (105) for achieving a fast lock time. The transceiver (104) has a reference oscillator (202) that generates a reference signal in a direct injection path and a modulator (206) coupled in the direct injection path modulates the reference signal to generate a modulated reference signal. A phase locked offset loop (220) coupled to the direct injection path generates a low frequency signal derived from the reference signal, a multiplier (210) coupled to the modulator (206) multiplies the modulated reference signal, and a mixer (214) coupled to the multiplier (210) receives the modulated reference signal in the direct injection path and an output signal from the phase locked offset loop (220) to generate a first local oscillator output signal and a modulated transmit carrier.
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