发明授权
US5754811A Instruction dispatch queue for improved instruction cache to queue timing
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指令调度队列,用于改进指令缓存到队列时序
- 专利标题: Instruction dispatch queue for improved instruction cache to queue timing
- 专利标题(中): 指令调度队列,用于改进指令缓存到队列时序
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申请号: US730606申请日: 1996-10-08
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公开(公告)号: US5754811A公开(公告)日: 1998-05-19
- 发明人: Michael Putrino , Soummya Mallick , Albert John Loper
- 申请人: Michael Putrino , Soummya Mallick , Albert John Loper
- 专利权人: International Business Machines Corp
- 当前专利权人: International Business Machines Corp
- 主分类号: G06F5/10
- IPC分类号: G06F5/10 ; G06F9/38 ; G06F9/00
摘要:
A circular dispatch queue is used to implement an instruction queue, in a microprocessor, in order to reduce the delay associated with the critical timing path between an instruction cache memory and the instruction queue. In the circular dispatch queue, instructions are never moved from one stage to another. Instead, pointers are maintained that indicate the top and bottom instructions within the circular dispatch queue. This technique removes inputs from the multiplexor between the register stages in the circular dispatch queue and the instruction cache memory, thus reducing the critical delay.
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