发明授权
- 专利标题: Synchronous memory with pipelined write operation
- 专利标题(中): 具有流水线写入操作的同步存储器
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申请号: US651873申请日: 1996-05-21
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公开(公告)号: US5761150A公开(公告)日: 1998-06-02
- 发明人: Seigoh Yukutake , Kinya Mitsumoto , Takashi Akioka , Masahiro Iwamura , Noboru Akiyama
- 申请人: Seigoh Yukutake , Kinya Mitsumoto , Takashi Akioka , Masahiro Iwamura , Noboru Akiyama
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX7-124709 19950524
- 主分类号: G11C11/413
- IPC分类号: G11C11/413 ; G06F12/00 ; G11C7/10 ; G11C8/06 ; G11C11/401 ; G11C11/407 ; G11C11/418 ; G11C8/00 ; G11C7/00
摘要:
There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
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