A system and method for emulating the state of a soft reset within a processor device without requiring a dedicated soft reset external pin associated with said processor device. The novel system includes control circuitry coupled to a processor device for detecting a number of conditions used to cause the processor device to execute a soft reset. In processor devices that contain a write-back cache, the soft reset signal resets the configuration of the processor device and returns the processor to "real-address mode" addressing, but does not destroy the contents of the write-back cache (unlike a regular reset). Upon detecting a soft reset attempt, the novel system generates a System Management Interrupt (SMI) which is responded to by an interrupt handling routine also of the novel system. This interrupt handling routine contains a set of configuration data (stored in memory) that represents the expected state of the processor device after a soft reset. The interrupt handling routine copies this set of configuration data into the processor device and returns. By copying the set of configuration data into the processor device, a soft reset is effectively emulated without the need for a dedicated soft reset pin. The novel system advantageously reduces the overall pin count of the processor device, or, alternatively, allows an additional signal to be supplied over the dedicated pin that was used by the prior art to implement the soft reset signal.