The present invention relates to a system and method for starting and maintaining a Central Processing Unit (CPU) clock even though the CPU clock is operating under a Clock Division Emulation (CDE) scheme. Break Events are broken into different groups with each group of Break Events being mapped to a particular programmable event timer. Each of the programmable event timers have an associated time limit which will keep the CPU clock running for a time commensurate with that group of Break Events. When a Break Event occurs, the programmable event timer associated with that particular Break Event will load the corresponding time limit into the programmable event timer. Once loaded, the programmable event timer will keep the CPU clock running during the entire time limit. Only after all of the programmable event timers have counted down will the CPU clock be allowed to stop.