Invention Grant
US5819072A Method of using a four-state simulator for testing integrated circuit
designs having variable timing constraints
失效
使用四态模拟器测试具有可变时序约束的集成电路设计的方法
- Patent Title: Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints
- Patent Title (中): 使用四态模拟器测试具有可变时序约束的集成电路设计的方法
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Application No.: US671432Application Date: 1996-06-27
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Publication No.: US5819072APublication Date: 1998-10-06
- Inventor: Louis B. Bushard , Peter B. Criswell , Douglas A. Fuller , James E. Rezek , Richard F. Paul
- Applicant: Louis B. Bushard , Peter B. Criswell , Douglas A. Fuller , James E. Rezek , Richard F. Paul
- Applicant Address: PA Blue Bell
- Assignee: Unisys Corporation
- Current Assignee: Unisys Corporation
- Current Assignee Address: PA Blue Bell
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455
Abstract:
Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.
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