发明授权
US5822334A High speed initialization system for RAM devices using JTAG loop for
providing valid parity bits
失效
用于RAM器件的高速初始化系统，使用JTAG环路提供有效的奇偶校验位
- 专利标题： High speed initialization system for RAM devices using JTAG loop for providing valid parity bits
- 专利标题（中）： 用于RAM器件的高速初始化系统，使用JTAG环路提供有效的奇偶校验位
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申请号： US583377申请日： 1996-01-05
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公开(公告)号： US5822334A公开(公告)日： 1998-10-13
- 发明人: Bruce Ernest Whittaker , James Henry Jeppesen, III
- 申请人： Bruce Ernest Whittaker , James Henry Jeppesen, III
- 申请人地址： PA Blue Bell
- 专利权人： Unisys Corporation
- 当前专利权人： Unisys Corporation
- 当前专利权人地址： PA Blue Bell
- 主分类号： G06F11/10
- IPC分类号： G06F11/10 ; G11C29/32 ; G06F11/00
摘要：
A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.
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