发明授权
US5826033A Parallel computer apparatus and method for performing all-to-all
communications among processing elements
失效
用于执行处理元件之间的所有通信的并行计算机装置和方法
- 专利标题: Parallel computer apparatus and method for performing all-to-all communications among processing elements
- 专利标题(中): 用于执行处理元件之间的所有通信的并行计算机装置和方法
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申请号: US982579申请日: 1992-11-27
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公开(公告)号: US5826033A公开(公告)日: 1998-10-20
- 发明人: Kenichi Hayashi , Takeshi Horie
- 申请人: Kenichi Hayashi , Takeshi Horie
- 申请人地址: JPX Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX3-310605 19911126
- 主分类号: G06F15/173
- IPC分类号: G06F15/173 ; G06F15/80 ; H04L12/407
摘要:
A parallel computer and all-to-all communications method. A plurality of processors are connected in an n-dimensional torus network, to provide an optimum communication method and apparatus for completing all-to-all communications within a shortest possible time. In the parallel computer having an n-dimensional rectangular parallelopiped torus network having a.sub.1 .times.a.sub.2 .times. . . . .times.a.sub.n processors, with the maximum value of a.sub.1, a.sub.2, . . . , a.sub.n defined as a.sub.max, it comprises a phase control unit having a phase control table for storing information according to which destination processors are determined for each of the predetermined transmission phases of a.sub.max P/4 (where P indicates the total number of processors) for a one-directional inter-processor connection channel, and of a.sub.max P/8 for a two-directional inter-processor connection channel, and a message transmission unit for transmitting a message to a destination processor listed in the phase control table during the phase in which the present processor is a source processor according to the predetermined phase order.
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