发明授权
US5828617A Multiple word width memory array clocking scheme for reading words from
a memory array
失效
用于从存储器阵列读取字的多字宽存储器阵列时钟方案
- 专利标题: Multiple word width memory array clocking scheme for reading words from a memory array
- 专利标题(中): 用于从存储器阵列读取字的多字宽存储器阵列时钟方案
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申请号: US852992申请日: 1997-05-08
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公开(公告)号: US5828617A公开(公告)日: 1998-10-27
- 发明人: Roland T. Knaack
- 申请人: Roland T. Knaack
- 申请人地址: CA San Jose
- 专利权人: Cypress Semiconductor Corp.
- 当前专利权人: Cypress Semiconductor Corp.
- 当前专利权人地址: CA San Jose
- 主分类号: G11C7/10
- IPC分类号: G11C7/10 ; G11C7/00
摘要:
The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.
公开/授权文献
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