In a DRAM, an upper address is assigned to each of ways W0 and W1, and a lower address is assigned to each word line WL in each of ways W0 and W1. A self-refresh start trigger generating circuit senses start of self-refresh, and a refresh address change sensing circuit senses change in an upper address. Based on the result of sensing, way selection signals RX0 and RX1 will not be reset and held at an active level while ways W0 and W1 are selected, respectively. Consequently, power consumption can be reduced compared to a conventional example in which signals RX0 and RX1 are reset every time a single word line WL is selected.