In an instruction processing unit, a first register group having at least one register whose bit width is enough for designating a desired address in the entire address space of a memory, and a second register group having at least one register whose bit width is not enough for said purpose, and operation means are provided. This operation means further includes first and second address generation means. In this unit, the first address generation means creates a desired operand address according to values stored in one or more registers in the first register group. The second address generation means creates an operand address to designate a desired partial space of the memory, by extending the bit width of a register in the second register group by a required amount.