发明授权
US5844271A Single layer polycrystalline silicon split-gate EEPROM cell having a
buried control gate
失效
具有埋置控制栅极的单层多晶硅分离栅极EEPROM单元
- 专利标题: Single layer polycrystalline silicon split-gate EEPROM cell having a buried control gate
- 专利标题(中): 具有埋置控制栅极的单层多晶硅分离栅极EEPROM单元
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申请号: US517495申请日: 1995-08-21
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公开(公告)号: US5844271A公开(公告)日: 1998-12-01
- 发明人: Rakesh Sethi , Wenchi Ting
- 申请人: Rakesh Sethi , Wenchi Ting
- 申请人地址: CA San Jose
- 专利权人: Cypress Semiconductor Corp.
- 当前专利权人: Cypress Semiconductor Corp.
- 当前专利权人地址: CA San Jose
- 主分类号: G11C16/04
- IPC分类号: G11C16/04 ; H01L27/115 ; H01L29/423 ; H01L29/788
摘要:
An electrically-erasable programmable read-only memory (EEPROM) cell includes a split-gate read transistor and a buried N-plate control gate. The split gate transistor includes a drain and source regions formed in a P-type silicon substrate with a channel formed therebetween. Silicon dioxide is disposed over the drain, channel and source regions wherein the oxide overlying the drain and a portion of the channel is thicker compared to the thickness of the oxide overlying the remainder of the channel and the source. A layer of polycrystalline silicon is disposed over the channel. The buried N-plate control gate is spaced laterally from the source, drain, and channel regions. The floating gate overlying the channel extends also over the buried N-plate control gate. The split gate structure effectively realizes a pair of in-series gates, each having a different threshold voltage in accordance with the thickness of the oxide used. The voltages applied to the N-plate region are capacitively coupled to the floating gate. The potential on the floating gate in turn causes activation of the transistors formed by the split-gate structure, depending on the existing charge on the floating gate.
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