发明授权
US5844914A Test circuit and method for refresh and descrambling in an integrated
memory circuit
失效
用于在集成存储器电路中刷新和解扰的测试电路和方法
- 专利标题: Test circuit and method for refresh and descrambling in an integrated memory circuit
- 专利标题(中): 用于在集成存储器电路中刷新和解扰的测试电路和方法
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申请号: US850807申请日: 1997-05-02
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公开(公告)号: US5844914A公开(公告)日: 1998-12-01
- 发明人: Heon-Cheol Kim , Hong-Sin Jun , Chang-Hyun Cho
- 申请人: Heon-Cheol Kim , Hong-Sin Jun , Chang-Hyun Cho
- 申请人地址: KRX Suwon
- 专利权人: Samsung Electronics, Co. Ltd.
- 当前专利权人: Samsung Electronics, Co. Ltd.
- 当前专利权人地址: KRX Suwon
- 优先权: KRX199616305 19960515; KRX199616306 19960515
- 主分类号: G11C11/401
- IPC分类号: G11C11/401 ; G01R31/28 ; G01R31/3181 ; G11C11/406 ; G11C29/08 ; G11C29/12 ; G11C29/18 ; G06F11/00
摘要:
A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.