A digital processor for simulating operation of a parallel processing array incorporates digital processing units (P.sub.1 to P.sub.8) communicating data to one another via addresses in memories (M.sub.0 to M.sub.8) and registers (R.sub.11 to R.sub.41). Each processing unit (e.g. P.sub.1) is programmed to input data and execute a computation involving updating of a stored coefficient followed by data output. Each computation involves use of a respective set of data addresses for data input and output, and each processing unit (e.g. P.sub.1) is programmed with a list of such sets employed in succession by that unit. On reaching the end of its list, the processing unit (e.g. P.sub.1) repeats it. Each address set is associated with a conceptual internal cell location in the simulated array (10), and each list is associated with a respective sub-array of the simulated array (10). Data is input cyclically to the processor (40) via input/output ports (I/O.sub.5 to I/O.sub.8) of some of the processing units (P.sub.5 to P.sub.8). Each processing unit (e.g. P.sub.1) executes its list of address sets within a cycle at a rate of one address set per subcycle. At the end of its list, each of the processing units (P.sub.1 to P.sub.8) has executed the functions associated with a conceptual respective sub-array of simulated cells (12), and the processor (40) as a whole has simulated operation of one cycle of a systolic array (10). Repeating the address set lists with further processor input provides successive simulated array cycles.