- 专利标题: Integrated circuit which uses a damascene process for producing staggered interconnect lines
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申请号: US655244申请日: 1996-06-05
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公开(公告)号: US5846876A公开(公告)日: 1998-12-08
- 发明人: Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
- 申请人: Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/522 ; H01L21/4763
摘要:
An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
公开/授权文献
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