Invention Grant
US5850532A Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched 失效
无效的指令扫描单元,用于检测与正在取出的指令相对应的无效预解码数据

Invalid instruction scan unit for detecting invalid predecode data
corresponding to instructions being fetched
Abstract:
An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.
Public/Granted literature
Information query
Patent Agency Ranking
0/0