发明授权
US5875392A Frequency mixer circuit receiving an unbalanced signal and outputting an output voltage having a minimized offset voltage 失效
接收不平衡信号并输出​​具有最小化的失调电压的输出电压的混频器电路

  • 专利标题: Frequency mixer circuit receiving an unbalanced signal and outputting an output voltage having a minimized offset voltage
  • 专利标题(中): 接收不平衡信号并输出​​具有最小化的失调电压的输出电压的混频器电路
  • 申请号: US705828
    申请日: 1996-08-30
  • 公开(公告)号: US5875392A
    公开(公告)日: 1999-02-23
  • 发明人: Toshiyuki Tanaka
  • 申请人: Toshiyuki Tanaka
  • 申请人地址: JPX Tokyo
  • 专利权人: NEC Corporation
  • 当前专利权人: NEC Corporation
  • 当前专利权人地址: JPX Tokyo
  • 优先权: JPX7-222387 19950830
  • 主分类号: H03D7/12
  • IPC分类号: H03D7/12 H03D7/14 H04B1/28
Frequency mixer circuit receiving an unbalanced signal and outputting an
output voltage having a minimized offset voltage
摘要:
A frequency mixer circuit comprises a first differential circuit composed of first and second transistors having common-connected emitters, and a second differential circuit composed of third and fourth transistors having common-connected emitters. A collector of the first transistor is connected to a collector of the third transistor and also connected through a first resistor to Vcc. A collector of the second transistor is connected to a collector of the fourth transistor and also connected through a second resistor to Vcc. A base of the first transistor is connected to a base of the fourth transistor, and a base of the second transistor is connected to a base of the third transistor. An emitter-grounded, fifth transistor is connected at its collector to the common-connected emitters of the first and second transistors, so as to constitute a current source for driving the first differential circuit. An emitter-grounded, sixth transistor is connected at its collector to the common-connected emitters of the third and fourth transistors, so as to constitute a current source for driving the second differential circuit. The base of the first to fourth transistors are biased with a first bias voltage, and a first high frequency signal is applied in the form of an unbalanced signal to the base of the first and fourth transistors. The base of the fifth and sixth transistors are biased with a second bias voltage, and a second high frequency signal is applied in the form of an unbalanced signal to the base of the fifth transistor.
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