An input circuit to a semiconductor device may selectively accept different voltage logic levels (e.g., TTL or CMOS) as selected by a preset selection signal. The selection signal activates an N-type or P-type transistor in the input circuit which alters the threshold switching voltage of the input circuit logic. By altering the input threshold voltage, both TTL and CMOS input signals may be correctly triggered. An additional circuitry may be provided to allow a low voltage circuit (e.g., 3.3 Volts) to be tolerant of higher voltage inputs (e.g., 5 Volts). An isolation transistor isolates the input of the circuit from the high voltage signal, while a pulldown transistor pulls a high logic, high voltage signal down to supply voltage level.