An apparatus and method for use in a semiconductor memory device to reduce internal circuit damage resulting from the effects of electro-static discharge (ESD) on a bitline pull-up or other type of circuit. Each of a plurality of bitlines in the memory device are coupled to a source terminal of a corresponding N-type MOSFET. Each source terminal is formed in a separate corner portion of at least one active region of the memory device, and is coupled to a given bitline via a bitline contact arranged in the corner portion. Each drain terminal of the N-type MOSFETS is formed from another portion of the active region and is coupled to a VDD supply of the memory device via a VDD contact. A gate terminal of a given MOSFET is formed from a polysilicon gate region overlying a channel in the active region. The gate region has an approximately 90.degree. bend therein such that a bitline contact in the corresponding corner portion of the active region is located between the bend and an outer peripheral edge of the corner portion. This layout allows the contact-to-diffusion-edge and contact-to-gate-edge spacings of the VDD contacts to be increased such that internal circuit ESD immunity of the memory device is improved without impacting device dimension and layout area constraints.