Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.