发明授权
- 专利标题： Voltage dropping circuit and integrated circuit
- 专利标题（中）： 降压电路和集成电路
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申请号： US977032申请日： 1997-11-25
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公开(公告)号： US5907237A公开(公告)日： 1999-05-25
- 发明人: Yasuhiko Sekimoto
- 申请人： Yasuhiko Sekimoto
- 申请人地址： JPX Hamamatsu
- 专利权人： Yamaha Corporation
- 当前专利权人： Yamaha Corporation
- 当前专利权人地址： JPX Hamamatsu
- 优先权： JPX8-316753 19961127
- 主分类号： G05F1/46
- IPC分类号： G05F1/46 ; G05F2/40
摘要：
A voltage dropping circuit is formed within an integrated circuit having at least one internal circuit, for dropping an external power supply voltage to generate a dropped voltage, and supplying the dropped voltage to the at least one internal circuit. A voltage divider divides the dropped voltage. A comparator compares the divided voltage with a reference voltage, and generates a control voltage according to a result of the comparison. A voltage generator generates the dropped voltage in response to the control voltage. A setting block sets a ratio of the divided voltage to the dropped voltage.
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