发明授权
- 专利标题: Wafer fabrication of die-bottom contacts for electronic devices
- 专利标题(中): 用于电子设备的芯片底部触点的晶片制造
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申请号: US788762申请日: 1997-01-24
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公开(公告)号: US5910687A公开(公告)日: 1999-06-08
- 发明人: Changsheng Chen , Phil P. Marcoux , Wendell B. Sander , James L. Young
- 申请人: Changsheng Chen , Phil P. Marcoux , Wendell B. Sander , James L. Young
- 申请人地址: CA San Jose
- 专利权人: ChipScale, Inc.
- 当前专利权人: ChipScale, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L23/485 ; H01L23/532 ; H01L23/52 ; H01L29/40
摘要:
A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. In one embodiment, a trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold wire extends from a connection point within the circuit into the trench. The gold wire may run over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back thinned to expose the bottom surface of the gold wire. Either the back thinning is selective so as to form a substrate standoff, or an epoxy standoff is applied to the bottom of the substrate. A solderable wire runs onto the standoff from the gold wire exposed on the protrusion, possibly over another insulation layer. If an insulative substrate is used, the insulation layers may be optional. Sawing separates the electronic devices and completes their fabrication, without a subsequent assembly step. In another embodiment, the trench in which the gold wires and the solderable wires connect is formed from the bottom of the substrate after it has been epoxy encapsulated. Optionally, the bottom surface of the substrate of the finished device drops down to be co-planar with the contact bottom surfaces, so as to conduct heat out of the device.
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