A structure and method for forming multiplication of a b-bit multiplicand X and a b-bit multiplier Y to generate a product P is disclosed. The present invention includes cells C.sub.mn configured in a b.times.b array, and pieces of means for generating partial product X.sub.mn, wherein outputs of the partial product generating means are connected to first inputs of the cells respectively. The second inputs of the cells C.sub.mn, where m=0, 1, 2, . . . , b-2, and n=1, 2, . . . , b-1, are connected to first outputs of the cells C.sub.m+1, n-1 respectively, and the second inputs of the cells C.sub.b-1, n, where n=1, 2, . . . , b-1, are connected to second outputs of the cells C.sub.n-1, b-1 respectively. Further, the third inputs of the cells C.sub.mn, where m=0, 1, 2, . . . , b-1, and n=2, 3, . . . , b-1, are connected to the second outputs of the cells C.sub.m, n-1. Therefore, a portion of the product P.sub.f, where f=0, 1, . . . , b-1, comes from the first outputs of the cells C.sub.0, f, another portion of the product P.sub.g, where g=b, b+1, . . . , 2b-1, comes from the first outputs of the cells C.sub.g-3, b-1, and a most significant bit P.sub.2b-1 of the product comes from the second output of the cell C.sub.b-1,b-1.