发明授权
US5923855A Multi-processor system and method for synchronizing among processors
with cache memory having reset state, invalid state, and valid state
失效
具有复位状态，无效状态和有效状态的高速缓冲存储器的处理器同步化的多处理器系统和方法
- 专利标题： Multi-processor system and method for synchronizing among processors with cache memory having reset state, invalid state, and valid state
- 专利标题（中）： 具有复位状态，无效状态和有效状态的高速缓冲存储器的处理器同步化的多处理器系统和方法
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申请号： US692346申请日： 1996-08-05
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公开(公告)号： US5923855A公开(公告)日： 1999-07-13
- 发明人: Takeshi Yamazaki
- 申请人： Takeshi Yamazaki
- 申请人地址： JPX Tokyo
- 专利权人： NEC Corporation
- 当前专利权人： NEC Corporation
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX7-204148 19950810
- 主分类号： G06F15/16
- IPC分类号： G06F15/16 ; G06F12/08 ; G06F15/163
摘要：
In a multi-processor system including a plurality of processing units each having a cache memory, the processing units each include a synchronization counter for indicating a present synchronization state of the respective processing unit, and a cache state table for holding information regarding the respective entries of the cache memory. The cache state table includes a cache state and a cache synchronization count. The cache state holds the respective cache state used in a cache protocol. The cache synchronization count holds a value of the synchronization counter when an entry is loaded. A cache protocol in the multi-processor system is simplified to realize a high-speed processing.
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